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k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 1 - 256mb network-dram specification version 0.7
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 2 - revision history version 0.0 (oct. / 5 / 2001) - first release version 0.1 (dec. / 15 / 2001) - the product name is changed to network-dram version 0.2 (jan. / 21 / 2002) - m-version is renamed to c-version - specify dc operating condition values - added power up sequence and power down(cl=4) timing diagrams version 0.3 (mar. / 23 / 2002) - the product name is changed to network ram - added speed bin (366mbps/pin,183mhz) version 0.4 (may. / 01 / 2002) - the product name is changed to network-dram - redefined i dd1s , i dd5 in dc characteristic version 0.5 (nov. /23 / 2002) -updated the current spec. value version 0.6 (apr. /9 / 2003) -changed idd2p value from 2ma to 3ma in page 10. -changed capacitance of dq/dqs version 0.7 (aug.31 / 2003) -changed tck max like below unit: pf from to min max min max capacitance(dq/dqs) 4.0 6.0 3.0 6.0 from to d4 da d3 d4 da d3 8.5 12 12 7.5 7.5 7.5
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 3 - general information organization d4 (400mbps) da (366mbps ) d3 (333mbps ) 256mx8 k4c560838c-tcd4 k4c560838c-tcda k4c560838c-tcd3 256mx16 k4c561638c-tcd4 K4C561638C-TCDA k4c561638c-tcd3 t : tsop ii (400mil x 875mil) d4 : 400bps/pin (200mhz, cl=4) da : 3 6 6 b p s / p i n ( 1 8 3 m h z , c l = 4 ) d3 : 333bps/pin (167mhz, cl=4) c : (commercial, normal) 08 : x8 16 : x16 56 : 256m 8k/64ms c : network-dram c : 4th generation k 4 c xx xx x x x - x x memory dram small classification density and refresh temperature & power package organization version interface (vdd & vddq) 1. samsung memory : k 2. dram : 4 3. small classification 4. density & refresh 5. organization 8. version 9. package 10. temperature & power 11. speed 3 : 4 bank 6. bank 1 2 3 4 5 6 7 8 9 10 11 xx 8 : sstl-2(2.5v, 2.5v) 7. interface (vdd & vddq) speed bank
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 4 - ? fully synchronous operation double data rate (ddr) data input/output are synchronized with both edges of dqs. differential clock (ck and ck )inputs cs , fn and all address input signals are sampled on the positive edge of ck. output data (dqs and dqs) is referenced to the crossings of ck and ck . ? fast clock cycle time of 5ns mini mum clock : 200mhz maximum data : 400mbps/pin maximum ? quad independent banks operation ? fast cycle and short iatency ? bidirectional data strobe signal ? distributed auto-refresh cycle in 7.8us ? self-refresh ? power down mode ? variable write length control ? write latency = cas latency - 1 ? programmable cas latency and burst length cas latency = 3, 4 burst length = 2, 4 ? organization k4c561638c-tc : 4,194,304 words x4 banks x 16 k4c560838c-tc : 8,388,608 words x4 banks x 8 ? power supply voltage vdd : 2.5 0.15v vddq : 2.5 0.15v ? 2.5v cmos i/o comply with sstl-2 (strong / normal / weaker / weakest) ? package 400x875mil, 66pin tsop ii, 0.65 mm pin pitch (tsop ii 66-p-400-0.65) item k4c560838/1638c-tc d4 (400mbps) da (366mbps) d3 (333mbps) t ck clock cycle time (min.) cl=3 5.5ns 6ns 6.5ns cl=4 5ns 5.5ns 6ns t rc random read/write cycle time (min.) 25ns 27.5ns 30ns t rac random access time (max.) 22ns 24ns 26ns i dd1s operating current (singl e bank) (max.) 310ma 300ma 290ma i dd2p power down current (max.) 2ma 2ma 2ma i dd6 self-refresh current(max.) 3ma 3ma 3ma key feature
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 5 - pin names pin name a0 to a14 address input ba0, ba1 bank address dq0 to dq7 (x8) data input/output dq0 to dq15 (x16) cs chip select fn function control pd power down control ck, (ck ) clock input dqs (x8) write/read data strobe udqs/ldqs (x16) vdd power(+2.5v) vss ground vddq power (+2.5v) (for i/o buffer) vssq ground (for i/o buffer) v ref reference voltage nc1,nc2 no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 400mil width 875mil length 66pin tsop ii 0.65mm lead pitch vdd vdd dq0 dq0 vddq vddq dq1 nc 2 dq2 dq1 vssq vssq dq3 nc 2 dq4 dq2 vddq vddq dq5 nc 2 dq6 dq3 vssq vssq dq7 nc 2 nc 1 nc 1 vddq vddq ldqs nc 2 nc 1 nc 1 vdd vdd nc 1 nc 1 nc 2 nc 2 a14 a14 a13 a13 fn fn cs cs nc 1 nc 1 ba0 ba0 ba1 ba1 a10 a10 a0 a0 a1 a1 a2 a2 a3 a3 vdd vdd vss vss dq7 dq15 vssq vssq nc 2 dq14 dq6 dq13 vddq vddq nc 2 dq12 dq5 dq11 vssq vssq nc 2 dq10 dq4 dq9 vddq vddq nc 2 dq8 nc 1 nc 1 vssq vssq dqs udqs nc 1 nc 1 vref vref vss vss nc 2 nc 2 ck ck ck ck pd pd nc 1 nc 1 a12 a12 a11 a11 a9 a9 a8 a8 a7 a7 a6 a6 a5 a5 a4 a4 vss vss k4c561638c-tc k4c560838c-tc pin assignment (top view)
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 6 - package outline drawing (t sop ii 66-p-400-0.65) 66 34 33 1 0.65 10.16 0.1 11.76 0.2 0.71typ + 0.08 0.24 - 0.07 0.13 m 1 0.1 1.2 max 0.1 0.05 22.62 max 22.22 0.1 0.1 0.5 0.1 0 ~ 10 0.8 0.2 0.145 0.055 unit in mm
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 7 - block diagram ck ck pd dll clock buffer command decoder cs fn control generator signal address buffer mode register upper address latch lower address latch column decoder row decoder bank #3 bank #2 bank #1 bank #0 memory cell array data control and latch circuit burst counter read data buffer write data buffer dq buffer a0 to a14 ba0, ba1 refresh counter write address latch address comparator dqs dq0 to dqn to each block note : the k4c560838c-tc configuration is 4 bank of 32768x256x 8 of cell array with the dq pins numbered dq0-7 the k4c561638c-tc configuration is 4 bank of 32768x128x16 of cell array with th e dq pins numbered dq0-15.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 8 - absolute maximum ratings caution : conditions outside the limits listed under "absolute maximum ratings" may cause pe rmanent damage to the device. the device is not meant to be operated under conditions outside the limits described in the operational section of this specifi - cation. exposure to "absolute maximum ratings" conditions for extended periods may affect device reliability. recommanded dc,ac operatin g conditions (notes : 1) (ta = 0 to 70 c) symbol parameter rating units notes vdd power supply voltage -0.3 to 3.3 v vddq power supply voltage (for i/o buffer) -0.3 to vdd + 0.3 v v in input voltage -0.3 to vdd + 0.3 v v out dq pin voltage -0.3 to vddq + 0.3 v v ref input reference voltage -0.3 to vdd + 0.3 v t opr operating temperature 0 to 70 o c t stg storage temperature -55 to 150 o c t solder soldering tem perature(10s) 260 o c p d power dissipation 1 w i out short circuit output current 50 ma symbol parameter min typ max units notes vdd power supply voltage 2.35 2.5 2.65 v vddq power supply voltage (for i/o buffer) 2.35 2.5 2.65 v v ref input reference voltage vddq /2*96% vddq/2 vddq/2*104% v 2 v ih (dc) input dc high voltage v ref +0.2 - vddq+0.2 v 5 v il (dc) input dc low voltage -0.1 - v ref -0.2 v 5 v ick (dc) differential clock dc i nput voltage -0.1 - vddq+0.1 v 10 v id (dc) input differential voltage. ck and ck inputs (dc) 0.4 - vddq+0.2 v 7,10 v ih (ac) input ac high voltage v ref +0.35 - vddq+0.2 v 3,6 v il (ac) input ac low voltage -0.1 - v ref -0.35 v 4,6 v id (ac) input differential voltage. ck and ck inputs (ac) 0.7 - vddq+0.2 v 7,10 v x (ac) differential ac input cross point voltage vddq/2-0.2 - vddq/2+0.2 v 8,10 v iso (ac) differential clock ac middle level vddq/2-0.2 - vddq/2+0.2 v 9,10
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 9 - 1. all voltages are referenced to vss, vssq. 2. v ref is expected to track variations in vddq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% of v ref (dc). 3. overshoot iimit : v ih (max.) = vddq + 0.9v with a pulse width <= 5ns 4. undershoot iimit : v il (min.) = -0.9v with a pulse width <= 5ns 5. v ih (dc) and v il (dc) are levels to maintain the current logic state. 6. v ih (ac) and v il (ac) are levels to change to the new logic state. 7. v id is magnitude of the difference between ck input level and ck input level. 8. the value of vx(ac) is expected to equal vddq/2 of the transmitting device. 9. v iso means [v ick (ck) + v ick (ck )]/2 10. refer to the figure below. notes : 11. in the case of external termination, vtt(term ination voltage) should be gone in the range of v ref (dc) 0.04v. pin capacitance (vdd, vddq = 2.5v, f = 1mhz, ta = 25 c ) note : these parameters are periodically sampled and not 100% tested. 2 the nc 2 pins have additional capacitance for adju stment of the adjacent pin capacitance. 1 the nc 2 pins have power and ground clamp. symbol parameter min max units c in input pin capacitance 2.5 4.0 pf c inc clock pin (ck, ck) capacitance 2.5 4.0 pf c i/o i/o pin (dq, dqs) capacitance 3.0 6.0 pf c nc 1 nc1 pin capacitance - 1.5 pf c nc 2 nc2 pin capacitance 4.0 6.0 pf clk clk v ss v id (ac) 0 v differential v iso v ss v ick v iso (min) v x v x v x v x v ick v ick v ick v iso (max) v x v id (ac)
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 10 - dc characteristics and operating conditions (vdd, vddq = 2.5v 0.15v, ta = 0~70 c ) notes : 1. these parameters depend on the cycle rate and these va lues are measured at a cycle rate with the minimum values of t ck , t rc and i rc . 2. these parameters depend on the output loading. the specified values are obtained with the output open. 3. refer to output driver characteristics for the detail. output driver strength is selected by extended mode regi ster. item symbol max units notes d4(400mbps) da(366mbps) d3(333mbps) operating current t ck = min, i rc =min read/write command cycling ov<=v in <=v il(ac) (max.) v ih(ac) (min.) <=v in <=vddq 1 bank operation, burst length = 4 address change up to 2 times during minimum i rc . i dd1s 310 300 290 ma 1, 2 standby current t ck =min, cs = v ih , pd = v ih , 0v<=v in <=v il(ac) (max.) v ih(ac) (min.)<=v ih <=vddq all banks : inactive state other input signals are changed one time during 4*t ck i dd2n 85 85 80 1 standby (power down) current t ck =min, cs = v ih , pd = v il (power down) 0v<=v in <=vddq all banks : inactive state i dd2p 222 1 auto-refresh current t ck = min, i refc = min, t refi = min auto-refresh command cycling 0v<=v in <=v il (ac) (max.), v ih (ac) (min.) <=v in <=vddq address change up to 2 times during minimum i refc . i dd5 105 100 95 1 self-refresh current self-refresh mode pd = 0.2v, ov<=v in <=vddq i dd6 333 item symbol min max unit notes input leakage current (0v<=v in <=vddq, all other pins not under test = 0v) i li -5 5 ua output leakage current (output disabled, 0v<=v out <=vddq) i lo -5 5 ua v ref current i ref -5 5 ua normal output driver output source dc current v oh = vddq - 0.4v i oh (dc) -10 - ma 3 output sink dc current v ol =0.4v i ol (dc) 10 - 3 strong output driver output source dc current v oh = vddq - 0.4v i oh (dc) -11 - 3 output sink dc current v ol =0.4v i ol (dc) 11 - 3 weaker output driver output source dc current v oh = vddq - 0.4v i oh (dc) -8 - 3 output sink dc current v ol =0.4v i ol (dc) 8- 3 weakest output driver output source dc current v oh = vddq - 0.4v i oh (dc) -7 - 3 output sink dc current v ol =0.4v i ol (dc) 7- 3
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 11 - ac characteristics and operating conditions (notes : 1, 2) symbol item d4(400mbps) da(366mbps) d3(333mbps) units notes min max min max min max t rc random cycle time 25 - 27.5 - 30 - ns 3 t ck clock cycle time cl = 3 5.5 7.5 6 7.5 6.5 7.5 3 cl = 4 5 7.5 5.5 7.5 6 7.5 3 t rac random access time - 22 - 24 - 26 3 t ch clock high time 0.45*t ck - 0.45*t ck - 0.45*t ck -3 t cl clock low time 0.45*t ck - 0.45*t ck - 0.45*t ck -3 t ckqs dqs access time from clk -0.65 0.65 -0.75 0.75 -0.85 0.85 3, 8 t qsq data output skew from dqs - 0.4 - 0.45 - 0.5 4 t ac data access time from clk -0.65 0.65 -0.75 0.75 -0.85 0.85 3, 8 t oh data output hold time from clk -0.65 0.65 -0.75 0.75 -0.85 0.85 3, 8 t qspre dqs(read) preamble pulse width 0.9*t ck -0.2 1.1*t ck +0.2 0.9*t ck -0.2 1.1*t ck +0.2 0.9*t ck -0.2 1.1*t ck +0.2 3 t hp clk half period ( minium of actual t ch , t cl )min(t ch , t cl ) - min(t ch , t cl ) - min(t ch , t cl ) - t qsp dqs(read) pulse width t hp -0.55 - t hp -0.6 - t hp -0.65 -4 t qsqv data output valid time from dqs t hp -0.55 - t hp -0.6 t hp -0.65 -4 t dqss dqs(write) low to high setup time 0.75*t ck 1.25*t ck 0.75*t ck 1.25*t ck 0.75*t ck 1.25*t ck 3 t dspre dqs(write) preamble pulse width 0.4*t ck - 0.4*t ck - 0.4*t ck -4 t dspres dqs first input setup time 0 - 0 - 0 - 3 t dspreh dqs first low input hold time 0.25*t ck - 0.25*t ck - 0.25*t ck -3 t dsp dqs high or low input pulse width 0.45*t ck 0.55*t ck 0.45*t ck 0.55*t ck 0.45*t ck 0.55*t ck 4 t dss dqs input falling edge to clock setup time cl = 3 1.3 - 1.4 - 1.5 - 3, 4 cl = 4 1.3 - 1.4 - 1.5 - 3, 4 t dspst dqs(write) postamble pulse width 0.45*t ck - 0.45*t ck 0.45*t ck -4 t dspsth dqs(write) postamble hold time cl = 3 1.3 - 1.4 - 1.5 - 3, 4 cl = 4 1.3 - 1.4 - 1.5 - 3, 4 t dssk udqs - ldqs skew (x16) -0.5*t ck 0.5*t ck -0.5*t ck 0.5*t ck -0.5*t ck 0.5*t ck t ds data input setup time from dqs 0.5 - 0.5 - 0.6 - 4 t dh data input hold time from dqs 0.5 - 0.5 - 0.6 - 4 t dipw data input pulse width (for each device) 1.5 - 1.5 - 1.9 - t is command / address input setup time 0.9 - 0.9 - 1 - 3 t ih command / address input hold time 0.9 - 0.9 - 1 - 3 t ipw command / address input pulse width (for each device) 2.0 - 2.0 - 2.2 - t lz data-out low impedance time from clk -0.65 - -0.75 - -0.85 - 3, 6, 8 t hz data-out high impedance time from clk - 0.65 - 0.75 - 0.85 3, 7, 8 t qslz dqs-out low impedance time from clk -0.65 - -0.75 - -0.85 - 3, 6, 8 t qshz dqs-out high impedance time from clk -0.65 0.65 -0.75 0.75 -0.85 0.85 3, 7, 8 t qpdh last output to pd high hold time 0 - 0 - 0 - t pdex power down exit time 2 - 2 - 2 - 3 t t input transition time 0.1 1 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry -0.5*t ck 5 -0.5*t ck 5 -0.5*t ck 53
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 12 - ac characteristics an d operating conditions (notes : 1, 2) (continued) symbol item d4(400mbps) da(366mbps) d3(333mbps) units notes min max min max min max t refi auto-refresh average interval 0.4 7.8 0.4 7.8 0.4 7.8 us 5 t pause pause time after power-up 200 - 200 - 200 - i rc random read/write cycle time (applicable to same bank) cl = 3 5 - 5 - 5 - cycle cl = 4 5 - 5 - 5 - i rcd rda/wra to lal command input delay (applicable to same bank) 111111 i ras lal to rda/wra command input delay (applicable to same bank) cl = 3 4 - 4 - 4 - cl = 4 4 - 4 - 4 - i rbd random bank access delay (applicable to other bank) 2-2-2- i rwd lal following rda to wra delay (applicable to other bank) bl = 2 2 - 2 - 2 - bl = 4 3 - 3 - 3 - i wrd lal following wra to rda delay (applicable to other bank) 1-1-1- i rsc mode register set cycle time cl = 3 5 - 5 - 5 - cl = 4 5 - 5 - 5 - i pd pd low to inactive state of input buffer - 1 - 1 - 1 i pda pd high to active state of input buffer - 1 - 1 - 1 i pdv power down mode valid from ref command cl = 3 15 - 15 - 15 - cl = 4 18 - 18 - 18 - i refc auto-refresh cycle time cl = 3 15 - 15 - 15 - cl = 4 18 - 18 - 18 - i ckd ref command to clock input disable at self-refresh entry 16 - 16 - 16 - i lock dll lock-on time (applicable to rda command) 200 - 200 - 200 -
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 13 - ac test conditions symbol parameter value units notes v ih (min) input high voltage (minimum) v ref + 0.35 v v il (max) input low voltage (maximum) v ref - 0.35 v v ref input reference voltage vddq/2 v v tt termination voltage v ref v v swing input signal peak to peak swing 1.0 v v r differential clock input reference level v x(ac) v v id (ac) input differential voltage 1.5 v slew input signal minimum slew rate 1.0 v/ns v otr output timing measurement reference voltage vddq/2 v v ih min (ac) v ref v il max (ac) v swing vddq vss z=50 ? r t =50 ? v tt cl=30pf v ref measurement point output output load circuit(sstl_2) slew=(v ih min (ac) - v il max (ac) )/ ? t ? t ? t notes : 1. transition times are measured between v ih min (dc) and v il max (dc) . transition (rise and fall) of input signals have a fixed slope. 2. if the result of nominal calculation with regard to t ck contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.75*t ck , t ck = 5ns, 0.75*5ns = 3.75ns is rounded up to 3.8ns.) 3. these parameters ar e measured from the diff erential clock (ck and ck ) ac cross point. 4. these parameters are meas ured from signal transition point of dqs crossing v ref level. 5. the t refi (max.) applies to equally distributed refresh method. the t refi (min.) applies to both burst refresh method and distributed refresh method. in such case, the average interval of ei ght consecutive auto-refresh commands has to be more than 400ns always . in other words, the number of auto- refres h cycles which can be performed within 3. 2us (8x400ns) is to 8 times in the maximum. 6. low impedance state is speified at vddq/2 0.2v from steady state. 7. high impedance state is sp ecified where output buffer is no longer driven. 8. these parameters depend on the clock jitter. these parameters are measured at stable clock. =0.5*vddq
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 14 - power up sequence 1. as for pd , being maintained by the low state (< 0.2v) is desirable before a power-supply injection. 2. apply vdd before or at the same time as vddq. 3. apply vddq before or at the same time as v ref . 4. start clock (ck, ck ) and maintain stable condition for 200us (min.). 5. after stable power and clock, apply desl and take pd = h. 6. issue emrs to enable dll and to define driver strength. (note : 1) 7. issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note : 1) 8. issue two or more auto -refresh commands. (note:1) 9. ready for normal operation after 200 clocks from extended mode register programming. (note : 2) note : 1. sequence 6, 7 and 8 can be issued in random order. 2. l=logic low, h = logic high desl rda mrs desl rda mrs desl wra ref wra ref desl desl emrs mrs op-code op-code hi-z v dd v ddq v ref clk clk pd command address dq dqs 200 s(min) t pda l rsc l rsc l refc 2.5v(typ) 2.5v(typ) 1.25v(typ) l refc t pdex 200 clock cycle(min) emrs mrs auto refresh cycle nomal operation
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 15 - t ck t ck t ch t cl t is t ih t ipw 1st t is t ih 2nd t is t ih 1st t is t ih 2nd t ipw t is t ih t ipw ua, ba t is t ih la t dipw t dipw t ds t dh t ds t dh ck ck cs fn a0-a14 ba0.ba1 dqs dq(input) ~ ~ basic timing diagrams timing of the ck, /ck refer to the command truth table. input timing t ch t cl t ck t t t t v ih v ih(ac) v il(ac) v il ck ck ck v ih v il v id(ac) ck v x v x v x ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 16 - q0 q1 q2 q3 lal (after rda) t ipw t is t ih t ch t cl t ck t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz postamble preamble t qslz t qspre t ckqs t qsp t qsp t qshz t ckqs t ckqs t qsq t lz t qsqv t ac t ac t ac t qsqv t qsq t hz t oh q0 q1 q2 q3 t lz t ac t ac t ac t qsqv t qsq t hz t oh t qsq t qsq t qsq t qsqv high-z high-z high-z high-z ck ck input (control & addresses) cas latency = 3 dqs (output) dq (output) dqs (output) dq (output) cas latency = 4 note : the correspondence of ldqs, udqs to dq. (k4c561638c-tc) ldqs dq0 to 7 udqs dq8 to 15 postamble preamble read timing (burst length = 4) high-z high-z
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 17 - d0 d1 d2 d3 lal (after wra) ck ck input (control & addresses) dqs (input) dq (input) t ipw t is t ih t ch t cl t ck t dqss t dspres t dsp t dsp t dsp t dspst t dss t dspsth postamble preamble t dss t dspre t ds t dh t ds t dh t ds t dh t dqss write timing (burst length = 4) cas latency = 3 d0 d1 d2 d3 dqs (input) dq (input) t dspres t dsp t dsp t dsp t dspst t dss t dspsth postamble preamble t dss t ds t dh t dipw t ds t dh t ds t dh t dqss cas latency = 4 t dss t dqss note. the correspondence of ldqs, udqs to dq. (k4c561638c-tc) ldqs dq0 to 7 udqs dq8 to 15 command ck ck input (control & addresses) t is t ih trefi, tpause, ixxxx timing t is t ih command t refi, t pause, i xxxx note. " i xxxx "means " i rc ", " i rcd ", " i ras ", etc. ~ ~ ~ ~ t dipw t dspre t dspreh t dspreh
k4c5608/1638c 256mb network-dram - 18 - rev. 0.7 aug. 2003 d0 d1 d2 d3 postamble preamble t dssk t ds t dh t ds t dh t ds t dh t ds t dh d0 d1 d2 d3 postamble preamble t ds t dh t ds t dh t dh t ds t dh d0 d1 d2 d3 wra ck ck input (control & addresses) ldqs dq0 ~ 7 postamble preamble write timing (x16 device) (burst length = 4) cas latency = 3 lal t dssk t dssk t dssk t dssk t ds t dh t ds t dh t ds t dh t ds t dh d0 d1 d2 d3 postamble preamble t ds t dh t ds t dh t ds t dh t ds t dh udqs dq8 ~ 15 ldqs dq0 ~ 7 cas latency = 4 udqs dq8 ~ 15 t dssk t dssk t dssk t ds
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 19 - function truth table (notes : 1,2,3) command truth table (notes : 4) ?the first command symbol function cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 desl device deselect h x x x x x x rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ?the second command (the next clock of rda or wra command) notes : 1. l = logic low, h = logic high, x = ei ther l or h, v = valid (specified value) , ba = bank address, ua = upper address , la = lower address. 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are latche d on the crossing point of di fferential clock input where clk goes to high. 4. operation mode is decided by the comination of 1st command and 2nd command refer to "state diagram" and the command table below. symbol function cs fn ba1-ba0 a14-a13 a12-a11 a10-a9 a8 a7 a6-a0 lal lower address latch (x16) h x x v v x x x la lal lower address latch (x8) h x x v x x x la la ref auto-refresh l x x x x x x x x mrs mode register set l x v l l l l v v read command table notes : 5. for x16 device, a7 is "x" (either l or h). command (symbol) cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h x x x x la la 5
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 20 - write command table k4c561638c-tc command (symbol) cs fn ba1-ba0 a14 a13 a12 a11 a10-a9 a8 a7 a6-a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h x x lvwo lvw1 uvw0 uvw1 x x x la k4c560838c-tc note : 6. a14 to a11 are used for variable wr ite length (vw) contro l at write operation. command (symbol) cs fn ba1-ba0 a14 a13 a12 a11 a10-a9 a8 a7 a6-a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h x x vwo vw1 x x x x la la vw truth table note : 7. for x16 device, lvw0 and lvw1 control dq0-dq7, uvw0 and uvw1 control dq8-dq15. function vw0 vw1 bl = 2 write all words l x write first one word h x bl = 4 reserved l l write all words h l write first two words l h write first one word h h mode register set command truth table note : 8. refer to "mode register table". command (symbol) cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes rda (1st) l h x x x x x mrs (2nd) l x v l l v v 8
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 21 - function truth table (continued) auto-refresh command table function command (symbol) current state pd cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes n-1 n active wra(1st) standby h h l l x x x x x auto-refresh ref(2nd) active h h l x x x x x x self-refresh command table function command (symbol) current state pd cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes n-1 n active wra(1st) standby h h l l x x x x x self-refresh entry ref(2nd) active h l l x x x x x x 9, 10 self-refresh continue - self-refresh l l x x x x x x x self-refresh exit selfx self-refresh l h h x x x x x x 11 power down table notes : 9. pd has to be brought to low within t fpdl from ref command. 10. pd should be brought to low after dq?s state turned high impedance. 11. when pd is brought to high from low, this function is executed asynchronously. function command (symbol) current state pd cs fn ba1-ba0 a14-a9 a8 a7 a6-a0 notes n-1 n power down entry pden standby h l h x x x x x x 10 power down continue - power down l l x x x x x x x power down exit pdex power down l h h x x x x x x 11
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 22 - function truth table (continued) notes : 12. illegal if any bank is not idle. 13. illegal to bank in specified states : function may be legal in the bank indicated by bank address (ba). 14. illegal if t fpdl is not satisfied. current state pd cs fn address command action notes n-1 n idle h h h x x desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h x x pden power down entry 12 h l l x x - illegal l x x x x - refer to power down state row active for read h h h x la lal begin read h h l x op-code mrs/emrs access to mode register h l h x x pden illegal h l l x x ref (self) illegal l x x x x - invalid row active for write h h h x la lal begin write h h l x x ref auto-refresh h l h x x pden illegal h l l x x ref (self) self-refresh entry l x x x x - invalid read h h h x x desl continue burst read to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h x x pden illegal h l l x x - illegal l x x x x - invalid write h h h x x desl data write & continue burst write to end 13 h h l h ba, ua rda illegal h h l l ba, ua wra illegal 13 h l h x x pden illegal h l l x x - illegal l x x x x - invalid auto-refreshing h h h x x desl nop-> idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h x x pden self-refresh entry h l l x x - illegal l x x x x - refer to self-refreshing state mode register accessing h h h x x desl nop-> idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h x x pden illegal 14 h l l x x - illegal l x x x x - invalid power down h x x x x - invalid l l x x x - maintain power down mode l h h x x rdex exit power down mode->idle after t pdex l h l x x - illegal se;f-refreshing h x x x x - invalid l l x x x - maintain self-refresh l h h x x selfx exit self-refresh->idle after i refc l h l x x - illegal
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 23 - mode register table regular mode register (notes : 1) address ba1 *1 ba0 *1 a14-a8 a7 *3 a6-a4 a3 a2-a0 register 0 0 0 tm cl bt bl a7 test mode (tm) 0 regular (default) 1 test mode entry a3 burst type (bt) 0 sequential 1 interleave a6 a5 a4 cas latency (cl) 00x reserved *2 010 reserved *2 011 3 100 4 101 reserved *2 11x reserved *2 a2 a1 a0 burst length (bl) 000 reserved *2 001 2 010 4 011 reserved *2 1xx extended mode register (notes : 4) address ba1 *4 ba0 *4 a14-a7 a6 a5-a2 a1 a0 register 0 1 0 dic 0 dic ds a6 a1 output driver impedance control (dic) 0 0 normal output driver 0 1 strong output driver 1 0 weaker output driver 1 1 weakest output driver a0 dll switch (ds) 0 dll enable 1 dll disable note : 1. regular mode register is chosen using the combination of ba0 = 0 and ba1 = 0. 2. "reserved" places in regular mode register should not be set. 3. a7 in regular mode register must be set to "0"(low state). because test mode is specific mode for supplier. 4. extended mode register is chosen usi ng the combination of ba0 = 1 and ba1 = 0.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 24 - state diagram self refresh power down standby (idle) mode register auto- refresh active (restore) active write (buffer) read pdex (pd = h) selfx (pd = h) pd = l pd = h lal lal ref mrs rda wra pden (pd = l) the second command at active state must be issued 1clock after rda or wra command input command input automatic return
k4c5608/1638c 256mb network-dram - 25 - rev. 0.7 aug. 2003 q0 q1 q0 q1 rda lal desl rda lal desl rda lal q0 q1 q2 q3 q0 q1 q2 q3 0 234567891011 1 i rc = 5 cycles i rc = 5 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles hi-z hi-z hi-z hi-z cl = 3 cl = 3 hi-z hi-z cl = 3 cl = 3 hi-z hi-z hi-z hi-z hi-z hi-z ck ck command dqs (output) bl = 2 dq (output) dqs (output) bl = 4 dq (output) q0 q1 q0 q1 rda lal desl rda lal desl rda lal q0 q1 q2 q3 q0 q1 q2 0 234567891011 1 i rc = 5 cycles i rc = 5 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles hi-z hi-z hi-z hi-z cl = 4 cl = 4 hi-z hi-z hi-z hi-z ck ck command dqs (output) bl = 2 dq (output) dqs (output) bl = 4 dq (output) timing diagrams single bank read timing (cl = 3) cl = 4 cl = 4 single bank read timing (cl = 4)
k4c5608/1638c 256mb network-dram - 26 - rev. 0.7 aug. 2003 wra lal desl wra lal desl wra lal d0 d1 0 234567891011 1 i rc = 5 cycles i rc = 5 cycles ck ck command dqs (input) bl = 2 dq (input) single bank write timing (cl = 3) d0 d1 d0 d1 d0 d1 d2 d3 d2 d3 i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle wl = 2 wl = 2 dqs (input) bl = 4 dq (input) t dqss t dqss t dqss wl = 2 wl = 2 wra lal desl wra lal desl wra lal d0 d1 0 234567891011 1 i rc = 5 cycles i rc = 5 cycles ck ck command dqs (input) bl = 2 dq (input) single bank write timing (cl = 4) d0 d1 d0 d1 d0 d1 d2 d3 d2 d3 i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle wl = 3 wl = 3 dqs (input) bl = 4 dq (input) t dqss t dqss wl = 3 wl = 3 note : means "h" or "l"
k4c5608/1638c 256mb network-dram - 27 - rev. 0.7 aug. 2003 d0 d1 q0 q1 rda lal desl wra lal desl rda lal q0 q1 q2 q3 d0 d1 d2 d3 0 234567891011 1 i rc = 5 cycles i rc = 5 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles hi-z hi-z hi-z hi-z cl = 3 wl = 2 hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z ck ck command dqs bl = 2 dq dqs bl = 4 dq single bank read-write timing (cl = 3) d0 d1 q0 q1 rda lal desl wra lal desl rda lal q0 q1 q2 q3 d0 d1 d2 d3 0 234567891011 1 i rc = 5 cycles i rc = 5 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles hi-z hi-z hi-z hi-z cl = 4 wl = 3 hi-z hi-z cl = 4 wl = 3 hi-z hi-z hi-z hi-z hi-z hi-z ck ck command single bank read-write timing (cl = 4) cl = 3 wl = 2 t dqss dqs bl = 2 dq dqs bl = 4 dq
k4c5608/1638c 256mb network-dram - 28 - rev. 0.7 aug. 2003 rdaa rdab 0 234567891011 1 i rc = 5 cycles i rbd = 2 cycles ck ck command multiple bank read timing (cl = 3) i ras = 4 cycles lala rdab lalb desl rdaa lala rdac lalc rdad lald bank"b" x bank"a" x bank"a" x bank"c" x bank"d" x bank"b" hi-z hi-z qa0 qa1 hi-z cl = 3 cl = 3 hi-z hi-z hi-z qb0 qb1 qa0 qa1 qc0 hi-z qa0 qa1 hi-z cl = 3 cl = 3 hi-z qb0 qb1 qc0 qa2 qa3 qb3 qb2 qa0 qa1 qa2 qa3 cl = 3 cl = 3 i rbd = 2 cycles i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rbd = 2 cycles i rbd = 2 cycles bank add. (ba0, ba1) dqs bl = 2 dq dqs bl = 4 dq (output) (output) (output) (output) rdaa rdab 0 234567891011 1 i rc = 5 cycles i rbd = 2 cycles ck ck command multiple bank read timing (cl = 4) i ras = 4 cycles lala rdab lalb desl rdaa lala rdac lalc rdad lald bank"b" x bank"a" x bank"a" x bank"c" x bank"d" x bank"b" hi-z hi-z qa0 qa1 hi-z cl = 4 cl = 4 hi-z hi-z hi-z qb0 qb1 qa0 qa1 hi-z qa0 qa1 hi-z cl = 4 cl = 4 hi-z qb0 qb1 qa2 qa2 qa3 qb3 qb2 qa0 qa1 cl = 4 cl = 4 i rbd = 2 cycles i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rcd =1 cycle i rbd = 2 cycles i rbd = 2 cycles bank add. (ba0, ba1) dqs bl = 2 dq dqs bl = 4 dq (output) (output) (output) (output) note : "x" is don?t care. i rc to the same bank must be satisfied.
k4c5608/1638c 256mb network-dram - 29 - rev. 0.7 aug. 2003 da0 da1 0 234567891011 1 ck ck multiple bank write timing (cl = 3) da0 da1 wl = 2 t dqss wraa wrab i rc = 5 cycles i rbd = 2 cycles i ras = 4 cycles lala wrab lalb desl wraa lala wrac lalc wrad lald bank"b" x bank"a" x bank"a" x bank"c" x bank"d" x bank"b" i rbd = 2 cycles i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rbd = 2 cycles i rbd = 2 cycles t dqss wl = 2 db0 db1 dc0 dc1 wl = 2 da0 da1 db0 db1 da2 da3 db3 db2 da0 da1 dc0 dc1 da2 da3 dc2 command bank add. (ba0, ba1) dqs bl = 2 dq dqs bl = 4 dq (input) (input) (input) (input) wl = 2 t dqss t dqss t dqss da0 da1 0 234567891011 1 ck ck multiple bank write timing (cl = 4) da0 da1 wl = 3 t dqss wraa wrab i rc = 5 cycles i rbd = 2 cycles i ras = 4 cycles lala wrab lalb desl wraa lala wrac lalc wrad lald bank"b" x bank"a" x bank"a" x bank"c" x bank"d" x bank"b" i rbd = 2 cycles i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rcd = 1 cycle i rbd = 2 cycles i rbd = 2 cycles t dqss wl = 3 db0 db1 dc0 wl = 3 da0 da1 db0 db1 da2 da3 db3 db2 da0 da1 dc0 da2 da3 command bank add. (ba0, ba1) dqs bl = 2 dq dqs bl = 4 dq (input) (input) (input) (input) wl = 3 t dqss t dqss t dqss dc1 dc1 note : means "h" or "l" "x" is don?t care i rc to the same bank must be satisfied.
k4c5608/1638c 256mb network-dram - 30 - rev. 0.7 aug. 2003 0 234567891011 1 ck ck multiple bank read-w rite timing (bl = 2) t dqss wraa lalc i rbd = 2 cycles lala rdab lalb desl wrac lalc rdad lald desl wrac bank"b" x bank"a" x bank"c" x bank"d" bank"c" x command bank add. (ba0, ba1) dqs cl = 3 dq dqs cl = 4 dq dc0 dc1 da0 da1 hi-z hi-z wl = 2 qb0 qb1 qd0 x i rcd = 1 cycle i rwd = 2 cycles i rbd = 2 cycles i rwd = 2 cycles i rc = 5 cycles i rcd = 1 cycle i wrd = 1 cycle i rcd = 1 cycle i wrd = 1 cycle i rcd = 1 cycle t dqss hi-z hi-z cl = 3 wl = 2 cl = 3 t dqss dc0 dc1 da0 da1 wl =3 qb0 qb1 t dqss hi-z hi-z cl = 4 wl = 3 cl = 4 hi-z hi-z hi-z hi-z multiple bank read-w rite timing (bl = 4) wl = 2 0 234567891011 1 ck ck wraa i rbd = 2 cycles lala rdab lalb wrac lalc rdad lald bank"b" x bank"a" x bank"c" x command bank add. (ba0, ba1) dqs cl = 3 dq da0 da1 hi-z hi-z qb0 qb1 i rcd = 1 cycle i rwd = 3 cycles i rbd = 2 cycles i rcd = 1 cycle i wrd = 1 cycle i rcd = 1 cycle i wrd = 1 cycle i rcd = 1 cycle t dqss t dqss desl x bank"d" desl da2 da3 qb2 qb3 dc0 dc1 dc2 dc3 t dqss t dqss cl = 3 hi-z wl = 2 cl = 3 hi-z wl = 3 dqs cl = 4 dq da0 da1 hi-z hi-z qb0 qb1 da2 da3 qb2 qb3 dc0 dc1 dc2 cl = 4 wl = 3 dc3 note : "x" is dont care i rc to the same bank must be satisfied.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 31 - 0 234567891011 1 ck ck single bank write with vw (cl=3, bl=4, sequential mode) desl wra lal wra lal lal command address dqs desl wra ua la=#3 ua la ua i rc = 5 cycles i rc = 5 cycles vw=2 la=#1 vw=1 d0 d1 d0 desl wra lal wra lal lal command desl wra ua la=#3 ua la ua lvw=1 d0 d1 d0 d0 d0 x8 device last two data are masked . last three data are masked . address #3 #0 (#1) (#2) #1 (#2) (#3) (#0) (input) dq (input) x16 device address udqs (input) dq8 to dq15 (input) ldqs (input) dq0 to dq7 (input) uvw=2 la=#3 lvw=1 uvw=1 last two data are masked . last three data are masked . address #3 #0 (#1) (#2) #1 (#2) (#3) (#0) address #3 (#0) (#1) (#2) #1 (#2) (#3) (#0) last three data are masked . last three data are masked . notes : dqs input must be continued till end of burst c ount even if some of laster data is masked.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 32 - q0 q1 rda lal desl rda mrs desl rda 0 234567891011 1 i rc = 5 cycles i rcs = 5 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle hi-z hi-z cl = 3 hi-z hi-z ck ck command mode register set timing (cl=3, bl=2) dqs dq or wra ba,ua la valid x a14 to a0 (op-code) ba,ua x ba0, ba1 (output) (output) q0 q1 rda lal desl x rda 0 234567n-1nn+1n+2 1 i pda = 1 cycles i rcd = 1 cycle t ih hi-z hi-z cl = 3 hi-z hi-z ck ck command power down timing (cl=3, bl=2) dqs dq or wra a14 to a0 ba0, ba1 (output) (output) desl ipd = 1 cycle t is t qpdh t pdex power down exit power down entry note : "x" is don?t care. ipd is defined from the first clock rising edage after pd is brought to "low". ipda is defined from the first clock rising edage after pd is brought to "high". pd must be kept "high" level until end of burst data output. pd should be brought to high within t refi(max) to maintain the data written into cell.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 33 - wra lal desl desl rda d0 d1 d2 d3 d1 0123456789n-1nn+1n+2 clk clk command pd bl=4 dqs (input) dq (input) bl=2 dqs (input) dq (input) x hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z or wra i rda = 1 cycle wl=3 2 clock cycles i rc (min), t refi (max) t ih t is i pd = 1 cycle d0 power down entry power down exit t pdex power down timing (cl=4) write cycle to power down mode note : "x" is don?t care. pd must be kept "high" level until wl+2 clock cycles from lal command. pd should be brought to high within t refi(max) to maintain the data written into cell.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 34 - q0 q1 rda lal desl wra ref desl lal or 0 234567891011 1 i rc = 5 cycles i refc = 15 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle hi-z hi-z cl = 3 hi-z hi-z ck ck command auto-refresh timing (cl=3, bl=4) dqs dq mrs or ref (output) (output) rda or wra q2 q3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ wra ref wra ref wra ref t 1 t 2 t 3 ck ~ ~ wra ref wra ref t 8 ~ ~ t 7 8 refresh cycle t refi = total time of 8 refresh cycle 8 t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 8 = t refi is specified to avoid partly concen trated current of refresh operation that is activated larger area than read/write operation. note : in case of cl=3, i refc must be meet 15 clock cycles. when t he auto-refresh oper ation is performed, the synthetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refresh cycles that is sampled randomly.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 35 - qx wra ref desl x *1 02345m-1mm+1 1 i refc t fpdl (min) hi-z ck ck command self-refresh entry timing dqs dq (output) (output) ~ ~ ~ ~ i rcd = 1 cycle t fpdl (max) t qpdh hi-z i ckd = 16 cycles *3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ note : 1. "x" is don?t care. 2. pd msut be brought to "low" within the timing between t fpdl (min) and t fpdl (max) to self refresh mode when pd is brought to "low" after i pdv , network-dram perform auto refr esh and enter power down mode. 3. it is desirable that clock input is continued at least 16 clock cycles from ref command even though pd is brought to "low" for self-refresh entry. pd x *1 desl *3 wra *5 ref *5 0 2 m-1 m m+1 m+2 n-1 n n+1 p-1 p 1 i refc i refc i pda = 1 cycle *4 i rcd = 1 cycle hi-z hi-z ck ck command self-refresh exit timing dqs dq (output) (output) ~ ~ desl command (1st) *6 command (2nd) *6 rda *7 lal *7 t pdex ircd = 1 cycle ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ pd note : 1. "x" is don?t care., 2. clock should be stable prior to pd = "high" if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to "high". 4. ipda is defined from the first clock rising edge after pd is brought to "high". 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda+lal) can be issued after ilock. ilock self-refresh exit auto refresh self refresh entry i pdv *2
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 36 - function description network-dram the network-dram is double data rate (ddr) operating. the netw ork-dram is competent to perform fast random core access, low latency, low consumption and high-speed data bandwidth. pin functions clock inputs : ck & ck the ck and ck inputs are used as the reference for synchronu s operation. ck is master clock input. the cs , fn and all address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck. the dqs and dq and dq output data are referenced to the crossing point of ck and ck . the timing reference point for the diff erential clock is when the ck and ck sig- nals cross during a transition. power down : pd the pd input controls the entry to the powe r down or self-refresh modes. the pd input does not have a clock suspend function like a cke input of a standard sdrams, therefore it is illegal to bring pd pin into low state if any read or write operation is bei ng per- formed. chip select & function control : cs & fn the cs and fn inputs are a control aignal for forming the operati on commands on network-dram. each operation mode is decided by the combination of the two cons ecutive operation commands using the cs and fn inputs. bank addresses : ba0 & ba1 the ba0 and ba1 inputs are latched at the ti me of assertion of the rda or wra command and are selected the bank to be used for the operation. ba0 ba1 bank #0 0 0 bank #1 1 0 bank #2 0 1 bank #3 1 1
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 37 - functional descri ption (continued) address inputs : a0 to a14 address inputs are used to access the arbi trary address of the memory ce ll array within each bank. the upper addresses with b ank address are latched at the rda or wra command and the lower addr esses are latched at the lal command. the a0 to a14 inputs are also used for setting the data in th e regular or extended mode register set cycle. data input/output : dq0 to dq7 or dq15 the input data of dq0 to dq15 are taken in synchr onizing with the both edges of dqs input signal. the output data of dq0 to dq15 ar e outputted synchronizing with the both edges of dqs output signal. data strobe : dqs or ldqs, udqs the dqs is bi-directional signal. both edges of dqs are used as the reference of data input or out put. the ldqs is allotted fo r lower byte (dq0 to dq7) data. the udqs is allotted for upper byte(dq8 to dq15) data. in write operation, the dqs used as an input sig nal is utilized for a latch of write data. in read operation, the dqs t hat is an output signal prov ides the read data strobe. power supply : vdd, vddq, vss, vssq vdd and vss are supply pins for memory core and peripheral circuits. vddq and vssq are power supply pins for the output buffer. reference voltage : v ref v ref is reference voltage for all input signals. upper address lower address k4c560838c-tc a0 to a14 a0 to a7 k4c561638c-tc a0 to a14 a0 to a6
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 38 - functional descri ption (continued) command functions and operations k4c5608/1638c-tc are introduced the two consccutive command input method. therefore, except for power down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with bank addresses and upper addresse s to the idle bank puts the bank designated by bank address in a read mode. when the lal command with lower addresses is issued at the next clock of the rd a command, the data is read out sequentially synchroniaing with the both edge s of dqs output signal (bur st read operation). the initial valid read data appears after cas latency, the burst length of read data and the burst type mu st be set in the mode register beforehand. the read operated ba nk goes back automatically to the idle state after i rc . write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addre sses to the idle bank puts the bank designated by bank address in a write mode. when the lal command with lower addresses is i ssued at the next clock of the wra command, the input data is latched sequentially synchronizing with the both edges of dqs inpu t signal (burst write operation). the data and dqs inputs hav e to be asserted in keeping with clock input afte r cas latency-1 from the issuing of the la l command. the write data length is set b y the vw in the lal command. the dqs have to be provided for a burst length. the cas latency and the burst type must be set in the mode register beforehand. the write operated bank goes back automatically to the idle state after i rc . auto-refresh operati on (1st command + 2nd command = wra + ref) k4c560838/1638c-tc are required to refresh like a standard sdra m. the auto-refresh operation is begun with the ref command following to the wra command. the auto-refresh mode can be effe ctive only when all banks are in the idle state and all outputs are in hi-z states. in a point to notice, th e write mode started with t he wra command is canceled by the ref command having gone in to the next clock of the wra command instea d of the lal command. the minimum period between the auto-refre sh command and the next command is specified by i refc . however, about a synthetic average interval of auto-refresh command, it must be careful. in case of equally distributed refresh, auto -refresh command has to be issued within once for every 7.8us by the maximum in case of burst refresh or random distributed refresh, the average interval of eight consecutiv e auto-refresh command has to be more than 400ns always. in other words, the number of auto-refresh cycles which c an be performed within 3.2us (8x400ns) is to 8 times in the maximum. self-refresh operation (1st command + 2nd command = wra + ref with pd ="l") it is the function of self-refresh operation that refresh op eration can be performed automatically by using an internal timer . when all banks are in the idle state and all outputs are in hi-z states, the k4c560838/1638c-tc become self -refresh mode by issuing the self- refresh command. pd has to be brought to "low" within t fpdl from the ref command following to the wra command for a self- refresh mode entry. in order to satisfy the refresh period, the self-r efresh entry command should be asserted within 7.8us aft er the latest auto-refresh command. once the device enters se lf-refresh mode, the desl command must be continued for i refc period. in addition, it is desirable that clock input is kept in i ckd period. the device is in self-refresh mode as long as pd held "low". during self-refresh mode, all input and output buffers except for pd are disabled, therefore the power dissipation lowers. regarding a self- refresh mode exit, pd has to be changed over from "low" to "high" along with the desl command, and the desl command has to be continuously issued in the numb er of clocks specified by i refc . the self-refresh exit function is asynchronous operation. it is required that one auto-refresh command is issued to av oid the violence of the refresh period just after i refc from self-refresh exit.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 39 - power down mode( pd ="l" ) when all banks are in the idle state and all outputs are in hi-z states, the k4c560838/1638c-t c become power down mode by asserting pd is "low". when the device enters the power down mode, all input and output buffers except for pd are disabled after specified time. therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to "high" and the desl command has to be issued at next ck rising edge after pd goes high. the power down exit function is asynchronous operation. mode register set (1st command + 2nd command = rda + mrs) when all banks are in the idle state, issuing the mrs command following to the rda command can program the mode register. in a point to notice, the read mode started with the rda command is canceled by the mrs comm and having gone into the next clock of t he rda command instead of the lal command. the data to be set in t he mode register is transferred us ing a0 to a14, ba0 and ba1 address inputs. the k4c560838/1638c-tc have two mode registers. these are regule and extended mode register. the regular or extended mode register is chosen by ba0 in the mrs command. the regular mode register desi gnates the operation mode for a read or write cycle. the regular mode register has four function fields. the four fields are as follows : (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lower address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has two function fields. the two fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable (e-2) output driver impedance control field. once these fields in the mode register are set up, the regist er contents are maintained until the mode register is set up agai n by another mrs command or power supply is lost. the initial value of the regular or extended mode register after power-up is unde- fined, therefore the mode regist er set command must be issued before proper operation.
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 40 - functional description (continued) ? regular mode regist er/extended mode register change bits (ba0, ba1) these bits are used to choose either regular mrs or extended mrs regular mode register fields (r-1) burst length field (a2 to a0) this field specifies the data length for column access using the a2 to a0 pins and sets the burst length to be 2 or 4 words. (r-2) burst type field (a3) this burst type can be chosen interleave mode or sequen tial mode. when the a3 bi t is " 0", sequential mode is selected. when the a3 bit is "1", inte rleave mode is selected. both burst types support burst length of 2 and 4 words. ? addressing sequence of sequential mode (a3) a column access is started from the inputted lower address and is performed by incrementing t he lower address input to the device. the address is varied by the burst length as the following. ba1 ba0 a14 - a0 0 0 regular mrs cycle 0 1 extended mrs cycle 1xreserved a2 a1 a0 burst length 000reserved 001 2 words 010 4 words 011reserved 1 x x reserved a3 burst type 0 sequential 1 interleave rda lal data 0 data 1 data 2 data 3 addressing sequence for sequential mode data access address burst length data 0 n 2 words (address bits is la0) not carried from la0 to la1 4 words(address bits is la1, la0) not carried from la0 to la1 data 1 n + 1 data 2 n + 2 data 3 n + 3 cas latency = 2 ck ck command dqs dq
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 41 - functional descri ption (continued) ? addressing sequence of inteleave mode a column access is started from t he inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode (r-3) cas latency field (a6 to a4) this field specifies the number of clo ck cycles from the assertion of the la l command following the rda command to the first data read. the minimum values of cas latency depends on the frequency of ck. in a write mode, the place of clock which should input write data is cas latency cycles - 1. (r-4) test mode field (a7) this bit is used to enter test mode for supplier only and must be set to "0" for normal operation. (r-5) reserved field in t he regular mode register ? reserved bits (a8 to a14) these bits are reserved for future operations. they must be set to "0" for normal operation. data access address burst length data 0 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words 4 words data 1 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 data 3 ...a8 a7 a6 a5 a4 a3 a2 a1 a0 a6 a5 a4 cas latency 000 reserved 001 reserved 010 reserved 011 3 100 4 101 reserved 110 reserved 111 reserved
k4c5608/1638c 256mb network-dram rev. 0.7 aug. 2003 - 42 - functional descri ption (continued) extended mode register fields (e-1) dll switch field (a0) this bit is used to enable dll. when the a0 bit is set "0", dll is enabled. (e-2) output driver imped ance control field (a1/a0) this field is used to choose output driver st rength. four types of dr iver strength are supported. (e-3) reserved field (a2 to a5, a7 to a14) these bits are reserved for future operations and must be set to "0" for normal operation. a6 a1 output driver impedance control 0 0 normal output driver 0 1 strong output driver 1 0 weaker output driver 1 1 weakest output driver

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